1. Field of the Invention
The present invention relates to an amplification type (or an active pixel type) solid-state imaging device and, more particularly, to a signal readout circuit of an amplification type solid-state imaging device which features a reduced per-pixel fixed pattern noise (FPN) and a reduced load capacitance of each horizontal signal line.
2. Description of the Related Art
Hitherto known as solid-state imaging devices (two-dimensional image sensors) are amplification type solid-state imaging devices (generally referred to as xe2x80x9cCMOS image sensorsxe2x80x9d) which are adapted to convert a signal charge generated in each pixel to a voltage signal or an electric current signal and amplify the signal within the pixel, and then read out the amplified signal by a scanning circuit, rather than directly read out the signal charge. In such an amplification type solid-state imaging device, each pixel has a configuration of horizontal type wherein a photo-electric conversion section and an amplification section are arranged in the same plane, or of vertical type wherein a photo-electric conversion section and an amplification section are three-dimensionally arranged.
One exemplary pixel configuration of the horizontal type is known as a APS type as shown in FIG. 8 (S. K. Mendis, etal., xe2x80x9cA 128xc3x97128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systemsxe2x80x9d, IEDM ""93, 583-586, December 1993). Referring to FIG. 8, a signal charge generated in a photo-electric conversion section 101 is transferred to the gate of a transistor 103 via a transistor 102 thereby to generate a voltage signal. In the transistor 103, the voltage signal is subjected to impedance conversion (current amplification), and the resulting signal Vsig is read out via a pixel selection switch 104. After the signal read-out, the signal charge accumulated at the gate of the transistor 103 is discharged to VD by a reset transistor 105.
One exemplary pixel configuration of the vertical type is known as a CMD type as shown in FIG. 9 (Nakamura, et al., xe2x80x9cGate Accumulation Type MOS Photo-transistor Image Sensorxe2x80x9d, Journal of Television Association, Vol.41, No. 11, pp. 1047-1053, 1987). Referring to FIG. 9, a signal charge generated by photo-electric conversion is accumulated at the channel region below the gate of a transistor 111. Then, a characteristic change of the transistor 111 due to the signal charge is read out as an output signal Vsig by applying a read-out voltage (xcfx86x) to the gate. That is, the photo-electric conversion, amplification and pixel selection are carried out in the transistor 111. For a reset operation, a voltage (xcfx86R) sufficiently higher than the read-out voltage is applied to the gate to discharge the signal charge to a substrate.
The pixels of the amplification type solid-state imaging device each having the configuration shown in FIG. 8 or 9 are each represented by a schematic diagram shown in FIG. 10. Herein, a pixel 131 carries out the photo-electric conversion, the amplification, the read-out and the reset operation. The read-out and the reset are controlled through signal lines xcfx86x and xcfx86R, respectively. An amplified signal Vsig is outputted from the pixel 131.
FIG. 11 illustrates an exemplary two-dimensional image sensor which employs the aforesaid pixels for the amplification type solid-state imaging device. The pixels 131 each have the same configuration as shown in FIG. 10. In a two-dimensional pixel region 140, the pixels 131 are two-dimensionally arranged. The read-out from the pixels 131 is controlled by a signal 143 from a first vertical scanning circuit 141, and the reset is controlled by a signal 144 from a second vertical scanning circuit 142. Output signals of each of the pixels (pixel signal) are applied to a correlated double sampling (CDS) circuit 150 provided in association with each vertical signal line to output a differential between a signal outputted at the read-out and a signal outputted at the reset. Therefore, variations in threshold among the pixels are eliminated for suppression of the per-pixel FPN.
The signal from the CDS circuit 150 is applied to an amplifier (column amplifier) 155, and held at an input side of the amplifier 155. The signal amplified by the amplifier 155 is controlled by a signal 161 from a horizontal scanning circuit 160 so as to be directed to a horizontal signal line 164 via a read-out switch 156. Since the read-out switches 156 are horizontally selected in sequence, signals from the respective amplifiers 155 are sequentially outputted to the horizontal signal line 164. The signals from the horizontal signal line 164 are each applied to an amplifier 169 for amplification thereof, and the amplified signals are each outputted as an output signal OS to a signal line 170.
However, the amplification type solid-state imaging device shown in FIG. 11, if having a greater horizontal pixel number, suffers from great difficulty in read-out. This will be explained with reference to a circuit diagram and a timing chart shown in FIGS. 11 and 12, respectively. It is herein assumed that the cycle of the clock xcfx86c of the horizontal scanning circuit 160 is T. A read-out pulse xcfx86H(j) is sequentially shifted by a width of T at an interval of T into a pulse xcfx86H(j+1), a pulse xcfx86H(j+2), a pulse xcfx86H(j+3) and the like to drive the read-out switches 156. If the horizontal read-out clock rate is increased with the increase of the horizontal pixel number, the cycle T is reduced. Since the number of the read-out switches 156 connected to the horizontal signal line 164 is increased, the load capacitance of the horizontal signal line 164 is increased. Therefore, the amplifiers 155 are required to drive the signal line 164 having a greater load in a shorter period T, so that a greater pixel number makes the driving more difficult. Further, it is also necessary to reduce the ON resistances of the read-out switches 156. In this case, however, there is a need to increase the size of the read-out switches 156, resulting in a further increase in the load capacitance of the horizontal signal line 164. This makes the driving further more difficult.
An approach to the aforesaid problem is described in Japanese Unexamined Patent Publication No.Hei 5(1993)-328224, which discloses an amplification type solid-state imaging device which includes a plurality of horizontal signal lines for parallel read-out. A block diagram of circuitry of the imaging device and a timing chart for the circuitry are shown in FIGS. 13 and 14, respectively. Referring to FIG. 13, each four vertical signal lines 145 are grouped, and respectively connected to four horizontal signal lines 164-1 to 164-4 via corresponding CDS circuits 150, read-out switches 156 and amplifiers 155. The CDS circuits 150 are each driven by a clamp pulse xcfx86C1 and a sample/hold pulse xcfx86S1, so that practical signal components with smaller variations among the pixels are outputted.
In this circuitry, the (2mxe2x88x921)-th switches or the (2m)-th switches (m: a positive integer) of the read-out switches 156 in each four-line group are connected in common to a horizontal scanning circuit 160, and driven by a pulse xcfx86H(1), xcfx86H(2), xcfx86H(3), . . . . As shown in FIG. 14, the pulse xcfx86H is shifted by a pulse width of 2T at an interval of T, wherein T is a clock cycle. Therefore, signals O1, O2, O3, O4, . . . are outputted from the respective vertical lines to the four horizontal signal lines S1, S2, S3 and S4, as shown in FIG. 14. Each two of the horizontal signal lines are combined by a switch 167-1 or 167-2, which is driven by a pulse xcfx86S or an inverted bar-xcfx86s, to provide an output OUT1 or OUT2. This is shown in FIG. 14. In this approach, the amplifiers 155 on the respective vertical signal lines are each read in a period of 2T with sufficient time. Further, the load capacitance of each of the horizontal signal lines are reduced to one fourth the load capacitance in the circuitry shown in FIG. 11, so that the driving load is reduced for easier high-speed driving.
However, the approach shown in FIGS. 13 and 14 suffers from the following problems. First, there are small variations in characteristic properties such as offset level and capacitance level among the horizontal signal lines. Accordingly, there remain some variations in the output signals OUT1 and OUT2 before these output signals are combined. Further, the two output signals OUT1 and OUT2 are ultimately provided, so that an additional signal combining process is required. This complicates the overall process, and inevitably entails variations in the two signals.
In view of the foregoing, the present invention is directed to an amplification type solid-state imaging device which ensures a higher horizontal read-out rate with the use of a plurality of horizontal signal lines while eliminating signal variations among the horizontal signal lines. Such an imaging device is capable of outputting a high quality image at a high speed while effectively suppressing the fixed pattern noise even at high speed read-out.
In accordance with the present invention, there is provided an amplification type solid-state imaging device, comprising: a pixel region including a plurality of amplification type photo-electric conversion elements arranged in a matrix array and each defining a pixel; vertical signal lines provided in a one-to-one correspondence with columns of the array in the pixel region for transmitting a pixel signal and a reference signal for each pixel; a plurality of horizontal signal lines; a horizontal scanning circuit for sequentially transmitting signal pairs each including the pixel signal and the reference signal from the respective vertical signal lines to the plurality of horizontal signal lines; a selection switch for sequentially switching the plurality of horizontal signal lines to selectively apply the signal pairs each including the pixel signal and the reference signal from the plurality of horizontal signal lines into a single common signal line; and a differential signal detection circuit for providing a differential signal between the pixel signal-and the reference signal in each of the signal pairs transmitted through the common signal line.
The amplification type solid-state imaging device of the present invention, which employs the plurality of horizontal signal lines, is adapted to read out the signal pairs in parallel from the plurality of horizontal signal lines. Therefore, the horizontal read-out speed is reduced, and the load capacitance of each of the horizontal signal lines is reduced. Even if the overall read-out speed is increased, proper driving of the imaging device can be ensured.
Further, the horizontal signal lines driven in parallel are finally combined into the single common signal line, from which a differential between the pixel signal and the reference signal from each of the horizontal signal lines is outputted. Therefore, even if signal variations among the respective horizontal signal lines occur due to differences in intrinsic characteristics among the horizontal signal lines, such signal variations can be eliminated, so that the resulting output signal is equivalent to that provided through a single horizontal line read-out operation.
Thus, the amplification type solid-state imaging device can effectively suppress the fixed pattern noise even at high speed read-out.